The present invention relates to a resin sealed semiconductor integrated circuit.
In a semiconductor integrated circuit chip (referred to as semiconductor chip hereinafter), a wiring layer of a metal film such as aluminum or copper or an alloy film led from bonding pads is used as a ground wiring or a power supply wiring for supplying an externally supplied power source potential to an internal circuit node. Due to the necessity of making resistance low and life until breakage due to electromigration long enough, practically, such power source wiring or ground wiring is made as wide as possible. Further, in order to prevent wirings connecting leads to bonding pads from being tangled, the bonding pads are arranged in a peripheral portion of the semiconductor chip. The wiring layer is coated with a passivation film of a hard material such as phospho-silicate glass (PSG) or silicon nitride to prevent errosion by water (water vapor). Then, the semiconductor chip is adhered to a metal plate called an island by means of conductive material and, after necessary connections are made by means of leads and wires, it is resin-sealed.
The passivation film functions to not only prevent water immigration but also to protect semiconductor circuit elements against contamination by substances contained in the sealing resin. Therefore, the thickness of the passivation film is designed to a value of about 1 .mu.m or more. With such large thickness of the passivation film, the latter on wiring layers tends to be cracked as pointed out in U.S. Pat. No. 4,467,345 issued to Ozawa on Aug. 21, 1984 and assigned to Nippon Electric Co., Ltd. This problem is due to the fact that grain size of the passivation film becomes larger on the wiring layers. This problem may be solved by limiting the width of wiring layer smaller than 50 .mu.m.
The crack problem of the passivation film as well as slide or destruction of the wiring layer also occurs in assembling step of the chip, such as resin sealing step. Such phenomena are due to difference in thermal expansion coefficient between a semiconductor chip and a resin seal. However, such problems are also solved by providing slits so that an effective width of portions of the wiring layer at corner portions of the semiconductor chip are made not less than 10 .mu.m and not more than 40 .mu.m, as disclosed in international publication Gazette WO 91/00616.
Further, such destruction and/or slide of wiring layers may occur during a heat cycle test for confirming reliability of a semiconductor chip under severe thermal conditions such as its use on a vehicle or in a desert, which is to be performed after resin sealing. This is solved by limiting the width of wiring layer not more than 5 .mu.m as disclosed in JP-A-62-174948. Since the width reduction of wiring layer necessarily increase possibility of breakage of wiring layer due to electromigration, it is usual to use a plurality of narrow parallel wiring layers instead of a single wide wiring layer. However, this approach, in which the width of each narrow wiring is not more then 5 .mu.m increases an area to be occupied by the wiring layers, causing an improvement of integration density to be difficult.
There is the trend, in the field of semiconductor integrated circuit, of both increase of integrated circuit scale and miniturization thereof. For example, for a semiconductor memory, while the number of bits for each memory element is increased at a rate of four times per several years, the increase of chip area is restricted to twice at most owing to miniturization of constitutional elements.
Further, recent power source current becomes substantially constant, say, 100 mA, regardless of bit number. The thickness of wiring layer tends to decrease with increase of bit number. Since electromigration depends upon current density, the width of wiring layer constituting a power source wiring and a ground wiring (the width is a total width of a plurality of narrow parallel wiring layers corresponding to a single wide wiring layer) can not be reduced with increase of bit number. This is obstructive to improvement of integration density of power source wiring and ground wiring. Such problem may be avoided by providing a plurality of conductor sets each including power source wiring, ground wiring and bonding pads. On the other hand, the number of lead wires increases necessarily with increase of semiconductor integrated circuit scale such as increase of bit number, while the number of leads per package is limited. Therefore, the above-mentioned approach is not preferable.
As other approaches than those mentioned above in which the width of wiring layer is reduced to prevent destruction or slide of wiring layers in a resin sealed semiconductor device, the following approaches are proposed:
A first approach is to coat the passivation film with polyimide film. Although this approach had been developed to prevent soft-error due to radiation, it has been found that this is also effective to relax stress exerted on a structure including the passivation film and the wiring layer to thereby prevent destruction or slide of the wiring layer. This method, however, requires the additional step of coating the passivation layer with polyimide film.
A second approach is to flatten a cover layer. That is, after a usual passivation film such as PSG film which has water repelling function and flatness of which is low is provided, a SOG (Spin-On-Glass) film is formed thereon to improve the surface flatness. With this method, it has been proved that, with such improved flatness, the destruction of wiring layer is reduced. The reason why such effect is provided is that, contrary to the stress relaxation of the polyimide film, the SOG film fills portions of the passivation film on side faces of wiring layer in which coverage is low and film thickness is small, causing mechanical strength to be increased. This method also requires such additional step.
These two methods have been not used widely for, not only the economical reason of requirement of additional step, but also reasons that manufacturers had neither effective techniques for formations of polyimide coating and passivation film having acceptable coverage nor knowledges of the aforementioned effects of the polyimide film and the flat cover film.
A method which has been used widely is to provide wiring layer on a chip except corners thereof and their peripheries where destruction of wiring layer may occur. On these portions of the chip, bonding pads and a minimum wiring layer may be provided. Since, in this conventional method, non-use portions may be left in a peripheral portion of the chip, the chip area is increased so that a minimum wiring layer might be destroyed.